System on-chip (SOC) circuitry includes static random access memory SRAM (e.g., used for cache memory). SRAM arrays (e.g., a cache) are configured such that the memory cells in the array maintain their state (logic 1 or logic 0) as long as power is supplied to the SRAM. SRAM arrays, such as a cache, operate at a minimum driving voltage (Vmin) to maintain the states of their memory cells and provide reliable results for operations (e.g., read operation, write operation).
Due to process variation, a single cell array typically includes several cells having a different Static Noise Margin (SNM). The SNM corresponds to the lowest driving voltage applied to a memory cell (due to the maximum amount of noise that may be accepted) in which the memory cell state may be preserved reliably. Accordingly, if the driving voltage of a cache falls below Vmin, defined as per the SNM of the least reliable cell(s) in the supported cache, the state of cells in the cache may not be maintained and the data (e.g., logic 1 or logic 0) in the cells may be lost (e.g., logic 1 may change to logic 0). Typically, the lowest driving voltage of the cache (Vmin) may be derived based on a low population of cells that have low SNM. For a conventional single-rail SRAM (single voltage applied to the SRAM), Vmin is applied across the logic on the voltage rail to maintain the state of the SRAM cells, significantly impacting the overall system's power consumption.